The present invention relates to an apparatus and method for processing a Picture-In-Picture (hereinafter "PIP") video signal, and more particularly to an apparatus and method for enhancing resolution of PIP displays on advanced TV receivers offering high definition and other enhanced display formats.
Generally, the PIP function, which is one of several available display functions on TV receivers, results in a sub-picture being displayed along with a main picture in the main picture area of the TV receiver. The sub-picture is vertically and horizontally compressed and displayed simultaneously with the main picture. In a conventional PIP function, a sub-picture video signal is displayed in one-third form that is compressed vertically and horizontally.
FIG. 1 is a block diagram illustrating an example of a conventional PIP processing apparatus. The conventional PIP apparatus includes an A/D converter 11, in which analog data of a sub-picture video signal V.sub.2 to be displayed simultaneously within the main picture is received and converted to a digital signal. A field memory 12 compresses vertically and horizontally the sub-picture video signal, which is input from the A/D converter 11, at a predetermined rate under the control of a controller 14. A D/A converter 13 converts a digital signal input from the field memory 12 to an analog signal and supplies the converted signal to a composite processor 15. The composite processor 15 processes a main-picture video signal V.sub.1 and a compressed sub-picture video signal and supplies the resulting composite signal V.sub.PIP to a display unit 16.
FIG. 2 is a view showing picture states, provided in order to explain the process used by the device of FIG. 1 for compressing a picture. It is based on a NTSC system having 525 interlaced scanning lines.
First, the sub-picture video signal V.sub.2 is input to the A/D converter 11. In the sub-picture video signal V.sub.2, prior to compression, as shown in FIG. 2A, a field has 262.5 vertical scanning lines, each one of which has a horizontal synchronization (sync) of 63.5 .mu.s. The A/D converter 11 converts an analog video signal of the sub-picture to a digital signal and supplies the converted signal to the field memory 12 one field at a time. Then, the controller 14 supplies a predetermined write clock CK.sub.W to the field memory 12. The field memory 12 stores the digital signal input in conformance with the write clock CK.sub.W. Field data stored in the field memory 12 is read out in conformance with a read clock CK.sub.R input from the controller 14 and is supplied to the D/A converter 13. The read clock CK.sub.R generated by the controller 14 is three times as fast as the write clock CK.sub.W. The video signal read from the field memory 12, shown in FIG. 2B, therefore has a form horizontally compressed to one-third size. In addition, the controller 14 reads out lines corresponding to every third line of each field stored in the field memory 12. That is, the controller 14 reads out only lines "1, 4, 7, . . . " from among the lines "1, 2, 3, . . . , 262.5" corresponding to each field. Therefore, the sub-picture video signal, as shown in FIG. 2C, is also compressed vertically to one-third size. Alternatively, it is possible to read out all stored lines after storing only every third line in the field memory 12. Thereafter, a compressed sub-picture video signal V.sub. 3 is supplied to an input terminal of the composite processor 15. The composite processor 15 composes a composite picture V.sub.PIP from the main-picture video signal V.sub.1 and the compressed sub-picture video signal V.sub.3 and outputs the composite signal V.sub.PIP. The composite signal V.sub.PIP output from the composite processor 15 is supplied to a display unit 16 and displayed on a TV receiver in a PIP form, such that the sub-picture is inserted into a particular portion of the main picture.
However, advanced systems, which scan progressively a video signal such as ED-TV, HD-TV etc., include the insertion of other scanning lines between lines. In general, a PIP display for advanced TV systems employs two methods. FIG. 3 is a schematic view for illustrating such conventional line interleaving methods. According to a first method, when the lines are read from the field memory, a line located in a position preceding the present interleaving line is read once more from the field memory, and used as the interleaving line to interleave the present field being compressed. Alternatively, one field of the sub-picture signal is additionally stored in the memory, and the line of the additionally stored field, the position of which is the same as the interleaving position of the present field, is read from the memory and used as the interleaving line to interleave the present field being compressed.
The interleaving line in the conventional PIP system is artificial data, not real video data. Therefore, several limitations arise to enhancing vertical resolution. In addition, the need arises for a line memory, field memory, control circuitry, and so on, in order to embody hardware for processing the interleaving signal. As a result, problems with expensive costs are encountered due to complexity of the circuitry system.